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DATA SHEET
PD45V128421, 45V128821, 45V128161
128M-BIT VirtualChannel DRAM
TM
MOS INTEGRATED CIRCUIT
Description
The 128M-bit VirtualChannel DRAM is implemented to be 100% pin and package compatible to the industry standard SDRAM. It uses the same command protocol and interface as SDRAM. It also follows the same electrical and timing specifications of the SDRAM, such that it is possible for one product platform to be used with the VirtualChannel DRAM and non-VirtualChannel DRAM part.
Features
* Fully Standard Synchronous Dynamic RAM, with all signals referenced to a positive clock edge * Dual internal banks controlled by Bank Select Address * Sixteen Channels controlled by Channel Select Address * Quad segments controlled by Segment Select Address * Byte control (x16) by LDQM and UDQM * Wrap sequence (Interleave) * Burst length (4) * Read latency (2) * Prefetch Read latency (4) : For x4 bits organization(PD45V128421), prefetch read operation can not be used. * Auto precharge and without auto precharge * Auto refresh and Self refresh * x4, x8, x16 organization * Single 3.3 V 0.3 V power supply * Interface: LVTTL * Refresh cycle: 4 K cycles / 64 ms
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for availability and additional information.
Document No. E0025N10 (1st edition) (Previous No. M15076EJ2V0DS00) Date Published January 2001 CP (K) Printed in Japan
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
PD45V128421, 45V128821, 45V128161
Ordering Information
Part number Organization (word x bit x bank) Clock frequency MHz (MAX.) Read latency Prefetch Read Latency 2 2 2 -
Note
Channel and Interface 16 channels and LVTTL
Package
PD45V128421G5-A75-9JF PD45V128821G5-A75-9JF PD45V128161G5-A75-9JF
16M x 4 x 2 8M x 8 x 2 4M x 16 x 2
133
54-pin Plastic TSOP(II) (10.16 mm (400))
4 4
Note For x4 bits organization, prefetch read operation can not be used.
2
Data Sheet E0025N10
PD45V128421, 45V128821, 45V128161
Part Number
[ x4, x8 ]
PD4 5 V 128 8 2 1 G5 - A75
NEC Memory DRAM
Category No letter : Single Data Rate SDRAM V : VirtualChannel Memory Minimum Cycle Time 75 : RL=2 : 7.5 ns (133 MHz) 10 : RL=2 : 10 ns (100 MHz)
Memory Density 64 : 128 : 64M bits 128M bits Low Voltage A : 3.3 0.3 V Organization Package 4 : x4 8 : x8 G5 : TSOP(II)
Number of Banks and Channel
Note Note Note Note Note
1 : 2 banks and 8 Channels 2 : 2 banks and 16 Channels 3 : 2 banks and 32 Channels 4 : 4 banks and 8 Channels 5 : 4 banks and 16 Channels 6 : 4 banks and 32 Channels
Interface 1 : LVTTL
Data Sheet E0025N10
3
PD45V128421, 45V128821, 45V128161
[ x16 ]
PD4 5 V 128 16 1 G5 - A75
NEC Memory DRAM
Category No letter : Single Data Rate SDRAM V : VirtualChannel Memory
Minimum Cycle Time 75 : RL=2 : 7.5 ns (133 MHz) 10 : RL=2 : 10 ns (100 MHz)
Memory Density 64 : 64M bits 128 : 128M bits Low Voltage A : 3.3 0.3 V Word and Number of Channel
Note Note
15 : x16 bits and 8 Channels 16 : x16 bits and 16 Channels 17 : x16 bits and 32 Channels
Package G5 : TSOP(II)
Number of Banks and Interface 1 : 2 Banks and LVTTL
4
Data Sheet E0025N10
PD45V128421, 45V128821, 45V128161
Pin Configurations
/xxx indicates active low signal.
[PD45V128421]
54-pin Plastic TSOP (II) (10.16 mm (400)) 16M words x 4 bits x 2 banks
VCC NC VCCQ NC DQ0 VSSQ NC NC VCCQ NC DQ1 VSSQ NC VCC NC /WE /CAS /RAS /CS Bank Address(A13) A12 Auto Precharge(A10) A0 A1 A2 A3 VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
VSS NC VSSQ NC DQ3 VCCQ NC NC VSSQ NC DQ2 VCCQ NC VSS NC DQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 VSS
A0 - A13 A0 - A12 A0 - A7, A10 DQ0 - DQ3 /CS /RAS /CAS /WE
: Address inputs : Row address inputs : Column address inputs : Data inputs / outputs : Chip select : Row address strobe : Column address strobe : Write enable
DQM CKE CLK VCC VSS VCCQ VSSQ NC
: DQ mask enable : Clock enable : System clock input : Supply voltage : Ground : Supply voltage for DQ : Ground for DQ : No connection
Remark Refer to 1. Input / Output Pin Function for Bank address, Channel address and Segment address.
Data Sheet E0025N10
5
PD45V128421, 45V128821, 45V128161
[PD45V128821] 54-pin Plastic TSOP (II) (10.16 mm (400)) 8M words x 8 bits x 2 banks
VCC DQ0 VCCQ NC DQ1 VSSQ NC DQ2 VCCQ NC DQ3 VSSQ NC VCC NC /WE /CAS /RAS /CS Bank Address(A13) A12 Auto Precharge(A10) A0 A1 A2 A3 VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
VSS DQ7 VSSQ NC DQ6 VCCQ NC DQ5 VSSQ NC DQ4 VCCQ NC VSS NC DQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 VSS
A0 - A13 A0 - A12 A0 - A7 DQ0 - DQ7 /CS /RAS /CAS /WE
: Address inputs : Row address inputs : Column address inputs : Data inputs / outputs : Chip select : Row address strobe : Column address strobe : Write enable
DQM CKE CLK VCC VSS VCCQ VSSQ NC
: DQ mask enable : Clock enable : System clock input : Supply voltage : Ground : Supply voltage for DQ : Ground for DQ : No connection
Remark Refer to 1. Input / Output Pin Function for Bank address, Channel address and Segment address.
6
Data Sheet E0025N10
PD45V128421, 45V128821, 45V128161
[PD45V128161] 54-pin Plastic TSOP (II) (10.16 mm (400)) 4M words x 16 bits x 2 banks
VCC DQ0 VCCQ DQ1 DQ2 VSSQ DQ3 DQ4 VCCQ DQ5 DQ6 VSSQ DQ7 VCC LDQM /WE /CAS /RAS /CS Bank Address(A13) A12 Auto Precharge(A10) A0 A1 A2 A3 VCC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
VSS DQ15 VSSQ DQ14 DQ13 VCCQ DQ12 DQ11 VSSQ DQ10 DQ9 VCCQ DQ8 VSS NC UDQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 VSS
A0 - A13 A0 - A12 A0 - A6 DQ0 - DQ15 /CS /RAS /CAS /WE
: Address inputs : Row address inputs : Column address inputs : Data inputs / outputs : Chip select : Row address strobe : Column address strobe : Write enable
UDQM LDQM CKE CLK VCC VSS VCCQ VSSQ NC
: Upper DQ mask enable : Lower DQ mask enable : Clock enable : System clock input : Supply voltage : Ground : Supply voltage for DQ : Ground for DQ : No connection
Remark Refer to 1. Input / Output Pin Function for Bank address, Channel address and Segment address.
Data Sheet E0025N10
7
PD45V128421, 45V128821, 45V128161
VirtualChannel DRAM Architecture
The VirtualChannel DRAM is a memory core technology designed to improve memory data throughput efficiency and initial latency of memories. Intended for use in next generation memory systems, the VirtualChannel DRAM technology is ideal memory for a wide range of application such as Multimedia PC, Game machine, Internet Server etc.... The slow core operation memory such as DRAM, Flash Memory and Mask ROM can get very significant performance improvements with VirtualChannel DRAM technology. Today's memory subsystems are accessed by multiple tasks/sources (memory masters), working in multitasking mode. Each memory master accesses memory with an address locality with a time locality, a block size and a number of contiguous accesses. VirtualChannel DRAM architecture is designed for this multitasking, multiple masters, interleaving access scenarios. The VirtualChannel DRAM provides memory masters with VirtualChannels. Each channel is a set of resources that constitute a fast dedicated path for each memory masters to access the memory. The VirtualChannels will minimize the overhead resulting from other memory master's accesses, reduce the access latency and facilitate automatic data sharing. Each channel is equipped with a data row buffer and its own independent operating modes. To the memory masters, this looks like its own very fast memory. The system memory controller associates these channels to the memory masters for their accesses. Thus, the channels are made to track the accesses of these memory masters. The system memory controller has complete controls over the operations of the channels. It can schedule and issue commands that causes segments of memory rows to be loaded into the channels or for data from the channels to be written back to the memory rows. Any channels can store the data from any rows, can be written to any rows and hence are fully associative. Then the Read and Write operations will be occurring as much as possible with these high speed channels, minimizing all overheads associated with the DRAM bank operations. The Read/Write operations of the channels (foreground operations) can operate independently with the DRAM bank operations (background operations) of Activate, Precharge, Prefetch (Loading row data to channel) and Restore (Writing channel data to row). Then VirtualChannel DRAM also further enhances performance by allowing the system memory controller to schedule the foreground and background operations to operate concurrently. VirtualChannel DRAM architecture offers the following features and benefits: 1. Multiplies the effective data throughput performance of conventional DRAM core. 2. Achieving close to full data bus bandwidth with low latency, interleaved random row, random column Read/Write through the channels. 3. Transparent DRAM bank operations through the concurrent foreground and Background Operations 4. Very wide (256 bytes wide) internal data transfer bus between Channel and memory core 5. Equivalence of tens of multiple memory banks by using only a fraction of the frequency of Row Activate and Precharge of conventional DRAM core.
8
Data Sheet E0025N10
PD45V128421, 45V128821, 45V128161
Block Diagram
Address
Address
Address Buffer and Refresh counter
Channel Control
Channel Selector Bank B Bank A
Segment Decoder
/CS
Memory Cell Array
Command Decoder
/RAS
/CAS
Control Logic
Row Decoder Data Control Circuit DQM
/WE
CKE CLK
Clock Generator
Latch Circuit
Input and Output Buffer
DQ
DQ
Column Decoder
Sense Amp.
Channel
Data Sheet E0025N10
9
PD45V128421, 45V128821, 45V128161
Conceptual Schematic 1
Background Prefetch Operation Restore Operation Foreground Read Operation Write Operation
Prefetch Operation (from Segment of memory core to Channel) Bank B Bank A
Segment Segment
16 Channels
Read Operation ( from Channel )
DQ
Segment
Segment
Row Decoder Row Decoder Restore Operation (from Channel to Segment of memory core)
Write Operation ( to Channel )
Segment
Segment
Segment
One segment : 1/4 Row One segment means one data transfer size at the background operations.
Input and Output Buffer
Segment
DQ
10
Data Sheet E0025N10
PD45V128421, 45V128821, 45V128161
Conceptual Schematic 2
Prefetch Operation
The data is fetched from a segment to any channel buffer.
Segment Segment
Bank A
16 Channels
Segment
Segment
Row Decoder
Segment
Bank B
Segment
Segment
Segment
Row Decoder
Restore Operation
The data is transferred from a channel buffer to any segment.
Segment
Bank A
Segment
Must select one channel
16 Channels
Segment
Row Decoder
Segment
Bank B
Segment
Segment
Segment
Row Decoder
Must select one segment
Segment
Data Sheet E0025N10
11
PD45V128421, 45V128821, 45V128161
Data size of segment and channel
1 Row
8 K (8192) bits
Memory cell
4 Segments
2 K (2048) bits
One segment means one data transfer size at the prefetch and restore operation.
16 Channels
2 K (2048) bits
1
2
3
4
5
16
x 4 bits organization
Column Selector
One channel density
2048 (2K) bits
512 bits
2048 (2K) bits / 4
Input and Output Buffer
0
1
2
3
x 8 bits organization
Column Selector
One channel density
2048 (2K) bits
256 bits
2048 (2K) bits / 8
Input and Output Buffer
0
1
2
3
4
5
6
7
x 16 bits organization
Column Selector
One channel density
2048 (2K) bits
128 bits
2048 (2K) bits / 16
Input and Output Buffer
0 1 2 3 4 5 6 7 8 9 10 1112 13 14 15
12
Data Sheet E0025N10
PD45V128421, 45V128821, 45V128161
1. Input / Output Pin Function
(1/3)
Pin name CLK Input/Output Input Function CLK is the master clock input. Other inputs signals for all commands are referenced to the CLK rising edge. CKE Input CKE determine validity of the next CLK (clock). If CKE is high, the next CLK rising edge is valid; otherwise it is invalid. If the CLK rising edge is invalid, the internal clock is not issued and the VirtualChannel DRAM suspends operation. When the VirtualChannel DRAM is not in burst mode and CKE is negated, the device enters power down mode. During power down mode, CKE must remain low. /CS Input Chip select. /CS low starts the command input cycle, which occurs on rising edge of CLK. During /CS high, commands are ignored but operations continue. /RAS, /CAS, /WE Input Command Inputs. The combination of these signals defines the command being entered. For details, refer to the Command Table in Command Functions. The symbol names (/RAS, /CAS, /WE) do not refer to the functional meanings used for conventional DRAM. DQM For x8,x4 devices UDQM LDQM For x16 device Input For x4, x8 devices DQM controls I/O buffers. For x16 device UDQM and LDQM control upper byte and lower byte I/O buffers, respectively. In read mode DQM controls the output buffers like a conventional /OE pin. DQM high and DQM low turn the output buffers off and on, respectively. The DQM latency for the read is two clocks. In write mode DQM controls the word mask. Input data is written to the memory cell if DQM is low but not if DQM is high. The DQM latency for the write is zero. DQ0 - DQ3 DQ0 - DQ7 DQ0 - DQ15 - (Power supply) Input / Output DQ pins have the same function as I/O pins on a Standard Synchronous DRAM. DQ0 - DQ3 (for x 4 bits device) DQ0 - DQ7 (for x 8 bits device) DQ0 - DQ8 (for x 16 bits device) NC VCC VSS VCCQ VSSQ (Power supply) VCCQ and VSSQ are power supply pins for the output buffers. No connection. Leave these pins unconnected. VCC and VSS are power supply pins for internal circuits.
Data Sheet E0025N10
13
PD45V128421, 45V128821, 45V128161
(2/3)
Pin name A0 - A13 Input / Output Input Function Address specification. These pins provide memory source and target addresses (bank, row, column, etc.), and channel addresses.
Row Address Row Address is determined by A0 - A12 at the CLK (clock) rising edge in the active command cycle. It does not depend on the bit organization.
Column Address Column Address is determined by A0 - A7 and A10 at the CLK rising edge in the read or write command cycle. It depends on the bit organization. : A0 - A7, A10 for x4 device : A0 - A7 for x8 device : A0 - A6 for x16 device.
Bank Address(A13) A13 is the bank select signal. In command cycle, A13 low select bank A, and A13 high select bank B.
Channel Address(A8, A9, A11, A12) A8, A9, A11, A12 are the channel select signals.
Channel number 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
A12 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
A11 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
A9 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
A8 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Segment Address(A0, A1, A10, A13) A0, A1, A10, A13 are the segment select signals. In prefetch and restore operations, column address in channel is determined by A0, A1. In prefetch read operation, segment is determined by A10, A13.
14
Data Sheet E0025N10
PD45V128421, 45V128821, 45V128161
(3/3)
Pin name A0 - A13 Input / Output Input Auto precharge Address(A10) A10 defines the precharge mode. Function
In the precharge command cycle High level: All banks are precharged. Low level: Only the bank selected by A13 is precharged.
In the prefetch or restore command cycle High level: Auto precharge Low level: Without auto precharge
Data Sheet E0025N10
15
PD45V128421, 45V128821, 45V128161
2. Truth Table 2.1 Command Execution
All commands are executed with the signal combination at the rising edge of the clock (CLK), /CS (Chip Select) must be low at the command input cycle. CKE (Clock Enable) must be high at one clock before the command input cycle as shown in below. The state of the /RAS, /CAS, and /WE signals specifies the command function to be executed. Some commands have the same signal combination for /RAS, /CAS, and /WE and are distinguished by some of address input signals. When /CS becomes high, operations continue as specified in the command, but further commands (signal states that would specify a command) are not registered until /CS becomes low. This state is Device deselect.
n-1 CLK n n+1
CKE
H
/CS /RAS /CAS /WE Address
L
Command
16
Data Sheet E0025N10
PD45V128421, 45V128821, 45V128161
2.2 Command Truth Table
Function Device deselect No operation Prefetch without auto precharge Prefetch with auto precharge Restore without auto precharge Restore with auto precharge Channel read Channel write Bank activate Prefetch read with auto precharge Precharge selected bank Precharge all banks Reset Symbol DESL NOP PFC PFCA RST RSTA READ WRIT ACT PFR PRE PALL REST
Note
/CS /RAS /CAS /WE A13 A12 A11 A10 H L L L L L L L L L L L L x H H H H H H H L L L L L x H H H H H L L H H L L L x H L L L L H L H L L L L x x x x x x x x L H L H
A9 x x
A8 x x
A7 x x L L H H
A6 x x L L x x
A5 x x L L x x
A4 x x x x x x
A3 x x x x x x
A2 x x x x x x
A1 x x
A0 x x
BA Cha. Cha. BA Cha. Cha. BA Cha. Cha. BA Cha. Cha. x L
Cha. Cha. Cha. Cha. Cha. Cha. Cha. Cha.
Seg. Seg. Seg. Seg. Seg. Seg. Seg. Seg.
Cha. Cha. Col. Cha. Cha. Col. Col. Col. Col. Col. Col. Col. Col. Cha. Cha. Col. Cha. Cha. Col. Col. Col. Col. Col. Col. Col. Col.
BA Row Row Row Row Row Row Row Row Row Row Row Row Row Seg. Cha. Cha. Seg. Cha. Cha. Col. Col. Col. Col. Col. Col. Col. Col. BA x L x x L x x L L H L x x L x x L x x L x x L L L H x x x x x x x x x x x x x x x
Note For x4 bits organization, this command is illegal. Remark H Abbreviations in the table mean as follows. : High level L : Low level X : High or Low level (Don' t care) Col. : Column address Seg. : Segment address BA : Bank Address
Row : Row address Cha. : Channel address
Data Sheet E0025N10
17
PD45V128421, 45V128821, 45V128161
2.3 CKE Truth Table
Current state Function Symbol CKE n-1 Activating Any Clock suspend Idle Idle Self refresh Clock suspend mode entry Clock suspend Clock suspend mode exit Auto refresh command Self refresh entry Self refresh exit - - - REF SELF - H L L H H L L Idle Power down Power down entry Power down exit - - H L n L L H H L H H L H x x x L L L H x H L x x x L L H x x x H x x x L L H x x x H x x x H H H x x x H x x x x x x x x x x /CS /RAS /CAS /WE Address
Remark H: High level, L: Low level, x: High or Low level (Don' t care)
18
Data Sheet E0025N10
PD45V128421, 45V128821, 45V128161
3. Commands
Device deselect (DESL) /CS /RAS /CAS /WE
High x x x
A13 A12 A11 A10 A9
x x x x x
A8
x
A7
x
A6
x
A5
x
A4
x
A3
x
A2
x
A1
x
A0
x
Remark x: High or Low level (Don' t care)
The device is deselected state by this command.
CLK CKE /CS /RAS /CAS /WE A0 to A13 H
Data Sheet E0025N10
19
PD45V128421, 45V128821, 45V128161
No operation (NOP)
/CS Low
/RAS High
/CAS High
/WE High
A13 x
A12 x
A11 x
A10 x
A9 x
A8 x
A7 x
A6 x
A5 x
A4 x
A3 x
A2 x
A1 x
A0 x
Remark x: High or Low level (Don' t care)
This command is not a execution command. No operations begin or terminate by this command.
CLK CKE /CS /RAS /CAS /WE A0 to A13 H
20
Data Sheet E0025N10
PD45V128421, 45V128821, 45V128161
Prefetch without auto precharge (PFC)
/CS Low
/RAS High
/CAS High
/WE Low
A13 BA
A12
A11
A10
A9
A8
A7
A6
A5
A4 x
A3 x
A2 x
A1
A0
Cha. Cha. Low Cha. Cha. Low Low Low
Seg. Seg.
Remark BA: Bank address, Cha.: Channel address, x: High or Low level (Don' t care), Seg.: Segment address
This command needs to follow Bank activate (ACT) command. This command fetches data from a segment of the activated row in a bank to a channel buffer which is chosen by channel address. The Segment and Bank fields specify the source segment and bank. In addition, the Channel Address field specifies the destination channel. A10 specify the optional precharge operation. In case of A10: low, without auto precharge operation occurs. In case of A10: high, with auto precharge operation occurs after data fetch operation. (Please refer to PFCA command.) (Bank precharge is necessary after data fetch.) This fetched command can be issued continuously without any precharge operation. For instance, when the first operation has been done from one of segment on activated row area to one of channel, if the second prefetch operation is required from same activated row, but different channel, the second prefetch command can be issued without any precharge operation. tPPD (PFC to PFC/PFCA command period) is required between first and second prefetch command. When the new row address area need to be activated on same bank, bank precharge is necessary after this PFC command. tPPL (PFC to PRE command period) is required between PFC and PRE. Fetched data into the channel buffer remains available for Channel Read and Channel Write operations.
CLK CKE /CS /RAS /CAS /WE A13 A12 A11 A10 A9 A8 A7 A6 A5 A2 to A4 A1 A0
Valid Valid Valid Valid
H
Bank select Channel address
Valid
Channel address
Valid
Segment address
Valid
Data Sheet E0025N10
21
PD45V128421, 45V128821, 45V128161
Prefetch with auto precharge (PFCA)
/CS Low
/RAS High
/CAS High
/WE Low
A13 BA
A12
A11
A10
A9
A8
A7
A6
A5
A4 x
A3 x
A2 x
A1
A0
Cha. Cha. High Cha. Cha. Low Low Low
Seg. Seg.
Remark BA: Bank address, Cha.: Channel address, x: High or Low level (Don' t care), Seg.: Segment address
This command needs to follow Bank activate (ACT) command. This command fetches data from a segment of the activated row in a bank to a channel buffer, and precharge operation is performed automatically, which closes the activated row after data fetch operation. The Segment and Bank fields specify the source segment and bank. In addition, the Channel Address field specifies the destination channel. A10 specify the optional precharge operation. In case of A10: low, without auto precharge operation occurs. (Please refer to PFC command.) In case of A10: high, with auto precharge operation occurs after data fetch operation. Fetched data into the channel buffer remains available for Channel Read and Channel Write operations.
CLK CKE /CS /RAS /CAS /WE A13 A12 A11 A10 A9 A8 A7 A6 A5 A2 to A4 A1 A0
Valid Valid Valid Valid
H
Bank select Channel address
Valid
Channel address
Valid
Segment address
Valid
22
Data Sheet E0025N10
PD45V128421, 45V128821, 45V128161
Restore without auto precharge (RST)
/CS Low
/RAS High
/CAS High
/WE Low
A13 BA
A12
A11
A10
A9
A8
A7
A6 x
A5 x
A4 x
A3 x
A2 x
A1
A0
Cha. Cha. Low Cha. Cha. High
Seg. Seg.
Remark BA: Bank address, Cha.: Channel address, x: High or Low level (Don' t care), Seg.: Segment address
This command transfers data from a channel buffer to a segment of a row which is going to be activated by following ACT command. The command Bank Address field specifies the destination bank. The Channel Address fields specify the source channel. The Segment number field specifies the destination segment. A10 specify the optional precharge operation. In case of A10: low, without auto precharge operation occurs. In case of A10: high, with auto precharge operation occurs after data fetch operation. (Please refer to RSTA command.)
CLK CKE /CS /RAS /CAS /WE A13 A12 A11 A10 A9 A8 A7 A2 to A6 A1 A0
Valid Valid Valid Valid
H
Bank select Channel address
Valid
Channel address
Valid
Segment address
Valid
Data Sheet E0025N10
23
PD45V128421, 45V128821, 45V128161
Restore with auto precharge (RSTA)
/CS Low
/RAS High
/CAS High
/WE Low
A13 BA
A12
A11
A10
A9
A8
A7
A6 x
A5 x
A4 x
A3 x
A2 x
A1
A0
Cha. Cha. High Cha. Cha. High
Seg. Seg.
Remark BA: Bank address, Cha.: Channel address, x: High or Low level (Don' t care), Seg.: Segment address
This command transfers data from a channel buffer to a segment of a row which is going to be activated by following ACT command. In addition, precharge operation is performed automatically which closes the active row after data restore operation. The command Bank Address field specifies the destination bank. The Channel Address fields specify the source channel. The Segment number field specifies the destination segment. A10 specify the optional precharge operation. In case of A10: low, without auto precharge operation occurs. (Please refer to RST command.) In case of A10: high, with auto precharge operation occurs after data fetch operation.
CLK CKE /CS /RAS /CAS /WE A13 A12 A11 A10 A9 A8 A7 A2 to A6 A1 A0
Valid Valid Valid Valid
H
Bank select Channel address
Valid
Channel address
Valid
Segment address
Valid
24
Data Sheet E0025N10
PD45V128421, 45V128821, 45V128161
Channel read (READ)
/CS Low
/RAS High
/CAS Low
/WE High
A13 x
A12
A11
A10
A9
A8
A7
A6 Col.
A5 Col.
A4 Col.
A3 Col.
A2 Col.
A1 Col.
A0 Col.
Cha. Cha. Col. Cha. Cha. Col.
Remark x: High or Low level (Don' t care), Cha.: Channel address, Col.: Column address
Channel Read (READ) reads data words from a channel buffer onto the data bus (DQ). The Channel Address field specifies the source channel. The Column Address field specifies the starting location of the data word in the buffer (Data words may be 4, 8, or 16 bits.).
CLK CKE /CS /RAS /CAS /WE A13 A12 A11 A10 A9 A8 A0 to A7
Valid
H
Channel address
Valid Valid Valid
Column address Channel address
Valid Valid
Column address
Data Sheet E0025N10
25
PD45V128421, 45V128821, 45V128161
Channel write (WRIT)
/CS Low
/RAS High
/CAS Low
/WE Low
A13
A12
A11
A10
A9
A8
A7
A6 Col.
A5 Col.
A4 Col.
A3 Col.
A2 Col.
A1 Col.
A0 Col.
Low Cha. Cha. Col. Cha. Cha. Col.
Remark x: High or Low level (Don' t care), Cha.: Channel address, Col.: Column address
Channel Write(WRIT) writes data from the data bus (DQ) into a channel buffer. The Channel Address field specifies the destination channel. The Column Address field specifies the starting location of the data word in the buffer (Data words may be 4, 8 or 16 bits.).
CLK CKE /CS /RAS /CAS /WE A13 A12 A11 A10 A9 A8 A0 to A7
Valid
H
Channel address
Valid Valid Valid
Column address Channel address
Valid Valid
Column address
26
Data Sheet E0025N10
PD45V128421, 45V128821, 45V128161
Bank activate (ACT)
/CS Low
/RAS Low
/CAS High
/WE High
A13 BA
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Row Row Row Row Row Row Row Row Row Row Row Row Row
Remark BA: Bank address, Row: Row address
Activation causes row contents to be placed into the bank's sense amplifier. The command Bank Address and Row Address fields specify bank and row. This device has two banks, each with 8,192 rows. This command activates the bank selected by bank address(A13) and a row address selected by A0 through A12. The row remains active for access until a Precharge command is issued to the bank. A Precharge command must be issued before another row can be activated in that bank. Each bank can have one row active. This command corresponds to a conventional DRAM's /RAS falling.
CLK CKE /CS /RAS /CAS /WE A13 A0 to A12
Valid Valid
H
Bank select Row address
Data Sheet E0025N10
27
PD45V128421, 45V128821, 45V128161
Prefetch read with auto precharge (PFR)
/CS Low
/RAS Low
/CAS High
/WE Low
A13
A12
A11
A10
A9
A8
A7
A6 Col.
A5 Col.
A4 Col.
A3 Col.
A2 Col.
A1 Col.
A0 Col.
Seg. Cha. Cha. Seg. Cha. Cha. Col.
Remark Seg.: Segment address, Cha.: Channel address, Col.: Column address
This command needs to follow Bank activate (ACT) command. This command fetches data from a segment of the activated row in a bank to a channel buffer, and reads data words from a channel buffer onto the data bus (DQ). In addition, precharge operation is performed automatically, which closes the activated row after data fetch operation. The Segment fields specify the source segment. In addition, the Channel Address field specifies the destination channel. The Column Address field specifies the starting location of the data word in the buffer (Data words may be 4, 8, or 16 bits.). For x4 bits organization, this command is illegal.
CLK CKE /CS /RAS /CAS /WE A13 A12 A11 A10 A9 A8 A0 to A7
Valid Valid
H
Segment address Channel address
Valid Valid Valid
Segment address Channel address
Valid Valid
Column address
28
Data Sheet E0025N10
PD45V128421, 45V128821, 45V128161
Precharge selected bank (PRE)
/CS Low
/RAS Low
/CAS Low
/WE Low
A13 BA
A12 x
A11 x
A10 Low
A9 x
A8 x
A7 x
A6 x
A5 Low
A4 x
A3 x
A2 x
A1 x
A0 x
Remark BA: Bank address, x: High or Low level (Don' t care)
This command closes (deactivates) an activated row in a bank, in order to prepare the bank for an Activate or Restore command to activate a new row. After precharging, a bank is in the Idle state. The Bank field specifies the bank to precharge and A10 Low specifies the command. After this command, tRP (precharge to activate command period) must be satisfied for next activate command to precharging bank. This command corresponds to a conventional DRAM's /RAS rising.
CLK CKE /CS /RAS /CAS /WE A13 A11,A12 A10 A6 to A9 A5 A0 to A4
Valid
H
Bank select
Data Sheet E0025N10
29
PD45V128421, 45V128821, 45V128161
Precharge all banks (PALL)
/CS Low
/RAS Low
/CAS Low
/WE Low
A13 x
A12 x
A11 x
A10 High
A9 x
A8 x
A7 x
A6 x
A5 Low
A4 x
A3 x
A2 x
A1 x
A0 x
Remark x: High or Low level (Don' t care)
The signal combination is Reserved (with command modifier A10 High). The PALL command is typically used during auto refresh operation and initialization. Replace with Precharge commands for each bank.
CLK CKE /CS /RAS /CAS /WE A11 to A13 A10 A6 to A9 A5 A0 to A4 H
30
Data Sheet E0025N10
PD45V128421, 45V128821, 45V128161
Reset (REST)
/CS Low
/RAS Low
/CAS Low
/WE Low
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4 x
A3 x
A2 x
A1 x
A0 x
Low Low Low Low Low Low Low Low High
Remark x: High or Low level (Don't care)
This command is used to initialize VirtualChannel DRAM.
CLK CKE /CS /RAS /CAS /WE A6 to A13 A5 A0 to A4 H
Data Sheet E0025N10
31
PD45V128421, 45V128821, 45V128161
Auto Refresh (REF)
CKE n-1 n
/CS
/RAS
/CAS
/WE
Address
High High
Low
Low
Low
High
x
Remark x: High or Low level (Don't care)
This command is a request to begin the auto refresh operation. The refresh address is generated internally. Before executing auto refresh, all banks must be in the idle state. After this cycle, all banks will be in the idle (precharged) state and ready for a row activate command. During tRC period (from refresh command to refresh or activate command), the VirtualChannel DRAM cannot accept any other command.
n-1 CLK CKE /CS /RAS /CAS /WE A0 to A13 H
n
H
32
Data Sheet E0025N10
PD45V128421, 45V128821, 45V128161
Self Refresh (SELF)
CKE n-1 n
/CS
/RAS
/CAS
/WE
Address
High Low
Low
Low
Low
High
x
Remark x: High or Low level (Don't care)
After the command execution, self refresh operation continues while CKE remains low. During self refresh mode, the internal refresh controller takes care of refresh interval and refresh operation. There is no need for external control. Before executing self refresh, both banks must be in the idle state. During self refresh mode, both background and foreground operation can not be executed.
n-1 CLK CKE /CS /RAS /CAS /WE A0 to A13 H
n
L
Data Sheet E0025N10
33
PD45V128421, 45V128821, 45V128161
4. Simplified State Diagram
Power Down
CKE:low CKE:high
IDLE Stand by
SELF SELF exit
REF
Self Refresh
RE
ST
Auto Refresh
Reset Active Power Down
E: low
AD RE
ACT
Write Suspend
WR
CK
E:lo w CK
AC
T
WR
IT
AC
T
AC
T
WRIT
W
WRIT
RSTA RST A
RI
WR
T
IT
ACT
Channel Write
READ
WRIT
Channel Read
CKE :
Row Active
RE
AD
high
IT
CK
h E:
igh
Read Suspend
RE
RE
RE
READ
AD
AD
AD
PFR
READ
PRE
RST
RST
PR E
RE
T
RS
Restore
with Auto Precharge
P
CKE :low
WRIT
Power ON
PRE
igh E:h CK
READ
Active stand by
REA
D
W RI T
Prefetch Read
PFCA CA PF
T RS
A
PF
PFC
PFC
PFC
CA
PF C
Restore
without Auto Precharge
Prefetch Precharge
PRE
without Auto Precharge
Prefetch
PFCA
with Auto Precharge
Automatic sequence Manual input foreground operation background operation
34
Data Sheet E0025N10
PD45V128421, 45V128821, 45V128161
5. Prefetch Read Operation ( Optional )
This operation fetches data from a segment of the activated row in a bank to a channel buffer, and reads data words from a channel buffer onto the data bus (DQ). In addition, precharge operation is performed automatically, which closes the activated row after data fetch operation. For x4 bits organization, prefetch read operation can not be used (PFR command is illegal).
Prefetch Operation Bank B Bank A
Segment Segment
16 Channels
Read Operation
DQ
Segment
Prefetch Read Operation
Segment
Row Decoder Row Decoder DQ
Segment
Segment
( Burst length = 4 )
0 CLK tAPD Command ACT PFC READ 1 2 3 4 5 6 7 8
Read latency = 2
Hi-Z
Input and Output Buffer
Segment
Segment
DQ
Q0
Q1
Q2
Q3
tAPRD Command ACT PFR
DQ
Hi-Z
Prefetch read latency = 4
Q0 Q1 Q2 Q3
The relationship between clock frequency and read latency, prefetch read latency
Clock frequency MHz(MAX.) 133 Read latency 2 Prefetch read latency 4
Data Sheet E0025N10
35
PD45V128421, 45V128821, 45V128161
6. Write Operation and Restore Operation
Write command proceeds write operation to the channel. When the system needs to refill the channel with new data, restore operation may be necessary. The restore operation needs both restore command and active command. Restore command must be first command. Restore operation is also fully associative operation. The data in the channel can be transferred to anywhere on memory core array. Another write and read operation to another channel can proceed during this restore operation. The another background operation is illegal while tRAD (RST/RSTA to ACT(R) command delay time). In addition, the foreground operation to the same channel set by RST command is illegal too.
DQ
16 Channels Bank B Bank A
Segment Segment Segment
Segment
Row Decoder Row Decoder Restore Operation (from Channel to Segment)
Write Operation ( to Channel )
Segment
Segment
Input and Output Buffer
Segment
Segment
DQ
( Burst length = 4 )
0 CLK tRCD Command WRIT 1 2 3 4 5 6 7 8 9 10
RST
tRAD
ACT (R)
tRAS
READ
PRE
Channel
Channel 1
Channel 1
Channel 1
Address A13 A10
Col. 0
Segment BankA
without Auto Precharge
Row 0
Col. 1 BankA
with Auto Precharge
BankA
BankA L
DQM
DQ
D1-0
D1-1
D1-2
D1-3
Hi-Z
Q1-1
Remark
ACT(R) command is ACT command after RST command.
36
Data Sheet E0025N10
PD45V128421, 45V128821, 45V128161
7. Basic Settings
After initialization, it automatically sets read latency, burst length and wrap sequence as followed.
Item Read latency Prefetch read Latency Burst length Wrap sequence
Value 2 4 4 Interleave
It cannot be set other value.
7.1 Burst Length and Sequence
[Burst of Four]
Starting Address (column address A1,A0) (binary) 00 01 10 11 Addressing Sequence Interleave (decimal) 0, 1, 2, 3 1, 0, 3, 2 2, 3, 0, 1 3, 2, 1, 0
Data Sheet E0025N10
37
PD45V128421, 45V128821, 45V128161
8. Initialization
The VirtualChannel DRAM is initialized in the power-on sequence according to the following. (1) To stabilize internal circuits, when power is applied, a 100 s or longer pause must precede any signal toggling. (2) After the pause, both banks must be precharged using the Precharge command (The Precharge all banks command is convenient). (3) Once the precharge is completed and the minimum tRP is satisfied, the reset command is executed one or more times (16 times execution also possible). (4) After the reset cycle, tRSC (2CLK minimum) pause must be satisfied as well. Two or more auto refresh must be performed. Remarks 1. The reset command and Refresh above may be transposed. 2. CKE and DQM must be held high until the Precharge command is issued to ensure data-bus Hi-Z.
38
Data Sheet E0025N10
PD45V128421, 45V128821, 45V128161
9. Electrical Specifications
* All voltages are referenced to VSS (GND). * After power up, wait more than 100 s and then, execute Power on sequence and Auto Refresh before proper device operation is achieved.
Absolute Maximum Ratings
Parameter Voltage on power supply pin relative to GND Voltage on input pin relative to GND Short circuit output current Power dissipation Operating ambient temperature Storage temperature Symbol VCC, VCCQ VT IO PD TA Tstg Condition Rating -0.5 to +4.6 -0.5 to +4.6 50 1 0 to 70 -55 to +125 Unit V V mA W C C
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter Supply voltage High level input voltage Low level input voltage Operating ambient temperature Symbol VCC, VCCQ VIH VIL TA Condition MIN. 3.0 2.0 -0.3 0
Note2
TYP. 3.3
MAX. 3.6 VCC + 0.3 +0.8 70
Note1
Unit V V V C
Notes 1. VIH (MAX.) = VCC + 1.5 V (Pulse width 5 ns) 2. VIL (MIN.) = -1.5 V (Pulse width 5 ns) Capacitance (TA = 25C, f = 1 MHz)
Parameter Input capacitance Symbol CI1 CI2 CLK A0 - A13, CKE, /CS, /RAS, /CAS, /WE, DQM, UDQM, LDQM Data input/output capacitance CI/O DQ 4.0 6.5 pF Test condition MIN. 2.5 2.5 TYP. MAX. 3.5 3.8 Unit pF
Data Sheet E0025N10
39
PD45V128421, 45V128821, 45V128161
DC Characteristics 1 (Recommended Operating Conditions unless otherwise noted)
Parameter Operating current ( Prefetch mode at one bank active ) Operating current ( Restore mode at one bank active ) Precharge standby current in power down mode Precharge standby current in non power down mode ICC2P CKE VIL(MAX.), tCK = 15 ns ICC2PS CKE VIL(MAX.), tCK = ICC2N CKE VIH(MIN.), tCK = 15 ns, /CS VIH(MIN.) Input signals are changed one time during 30 ns. ICC2NS CKE VIH(MIN.), tCK = , Input signals are stable. Active standby current in power down mode Active standby current in non power down mode ICC3P CKE VIL(MAX.), tCK = 15 ns ICC3PS CKE VIL(MAX.), tCK = ICC3N CKE VIH(MIN.), tCK = 15 ns, /CS VIH(MIN.) Input signals are changed one time during 30 ns. ICC3NS CKEVIH(MIN.),tCK=, Input signals are stable. Operating current (Burst mode) Auto refresh current Self refresh current ICC5 ICC6 ICC4 tCK tCK(MIN.), IO = 0 mA, Background: precharge standby tRCF tRCF(MIN.) CKE 0.2 V 230 2 mA mA 3 60 20 65 75 mA 2 10 6 6 30 mA mA 1.2 1.2 20 mA mA ICC1R tRC tRC(MIN.) 150 mA 1 Symbol ICC1P tRC tRC(MIN.) Prefetch is executed one time during tRC. Test condition x4 Maximum. x8 x16 150 Unit Notes mA 1
Notes 1. ICC1 depends on cycle rates. In addition to this, ICC1 is measured on condition that addresses are changed only one time during tCK(MIN.). 2. ICC4 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, ICC4 is measured on condition that addresses are changed only one time during tCK(MIN.). 3. ICC5 is measured on condition that addresses are changed only one time during tCK(MIN.).
DC Characteristics 2 (Recommended Operating Conditions unless otherwise noted)
Parameter Input leakage current Output leakage current High level output voltage Low level output voltage Symbol II(L) IO(L) VOH VOL Test condition 0 VI VCCQ, VCCQ = VCC All other pins not under test = 0 V 0 VO VCCQ, DOUT is disabled. IO = - 4 mA IO = + 4 mA - 1.5 2.4 - - - - + 1.5 - 0.4 MIN. - 1.0 TYP. - MAX. + 1.0 Unit Note
A A
V V
40
Data Sheet E0025N10
PD45V128421, 45V128821, 45V128161
AC Characteristics (Recommended Operating Conditions unless otherwise noted)
Test Conditions * AC measurements assume tT = 1 ns. * Reference level for measuring timing of input signals is 1.4 V. Transition times are measured between VIH and VIL. * If tT is longer than 1 ns, reference level for measuring timing of input signals is VIH(MIN.) and VIL(MAX.). * An access time is measured at 1.4 V.
tCK2 tCH CLK tCKS CKE tS Command Address DQM tH tCKH tCL tCH tCK2 tCL
(Input)
Valid tDS tDH tDS tDH
Data (Input) tAC2 tLZ Hi-Z
Valid tAC2 tOH2
Valid
tHZ Hi-Z
Data (Output)
Valid
Valid
Data Sheet E0025N10
41
PD45V128421, 45V128821, 45V128161
AC characteristics
Parameter Symbol -A75 MIN. Clock cycle time Access time from CLK CLK high level width CLK low level width Data-out hold time Data-out low-impedance time Data-out high-impedance time Data-in setup time Data-in hold time Address, Command, DQM setup time Address, Command, DQM hold time CKE setup time CKE hold time CKE setup time (Power down exit) Transition time Refresh time (4,096 refresh cycle) Reset cycle time tCK2 tAC2 tCH tCL tOH tLZ tHZ2 tDS tDH tS tH tCKS tCKH tCKSP tT tREF tRSC 7.5 - 2.5 2.5 2.7 0 2.5 1.5 0.8 1.5 0.8 1.5 0.8 1.5 0.5 - 2 MAX. - 5.4 - - - - 5.4 - - - - - - - 30 64 - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms CLK 1 1 Unit Note
Note1 Output load.
Z = 50 Output 50 pF
42
Data Sheet E0025N10
PD45V128421, 45V128821, 45V128161
AC characteristics (Background to Background operation)
Parameter Symbol -A 75 MIN. MAX. SAME BANK OPERATION ACT to ACT / REF Command period REF to REF / ACT Command period ACT to PRE Command period PRE to ACT / REF Command period ACT to PFC / PFCA Command delay time ACT to PFR Command delay time (Prefetch Read Operation) PFC to PRE Command delay time PFCA / PFR to ACT / REF Command delay time RST / RSTA to ACT(R)
Note1
Unit
Notes
tRC tRCF tRAS tRP tAPD tAPRD tPPL tPAL tRAD
67.5 67.5
- -
ns ns ns ns ns ns ns ns ns 3 2
52.5 120,000 20 15 15 22.5 45 7.5 - - - - - 30
Command delay time
SAME,OTHER BANK OPERATION ACT(R)
Note1
to PFC/PFCA/PFR
tRPD tPPD
37.5 22.5
- -
ns ns
Command delay time PFC to PFC / PFCA Command delay time
OTHER BANK OPERATION ACT to ACT / ACT(R) or ACT(R) to ACT Command delay time ACT(R) to ACT(R) Command delay time PFC / PFCA to RST / RSTA Command delay time tRRD tRRDR tPRD 15 30 22.5 - - - ns ns ns
Notes 1. ACT(R) command is ACT command after RST command. 2. For x4 bits organization, prefetch read operation can not used. 3. The another background operation and same channel foreground operation are illegal while tRAD period.
Data Sheet E0025N10
43
PD45V128421, 45V128821, 45V128161
AC characteristics (Foreground to Foreground operation)
Parameter Symbol -A 75 MIN. READ / WRITE to READ / WRITE Command delay time tCCD 7.5 MAX. - ns Unit Note
AC characteristics (Background to Foreground operation) (after same channel Prefetch/Restore)
Parameter Symbol -A 75 MIN. PFC / PFCA to READ / WRITE Command delay time ACT(R) to READ / WRITE Command delay time tPCD tRCD 15 30 MAX. - - ns ns 1 Unit Note
Note1 ACT(R) command is ACT command after RST command.
44
Data Sheet E0025N10
PD45V128421, 45V128821, 45V128161
Power on Sequence and Auto Refresh
0 CLK 1 2 3 4 12 13 21 22
Command
PALL
REST
REF
REF
ACT
tRP Address
tRSC
tRCF
tRCF
Row 1
A10
H
BankA
A5
L
DQM
DQ
Hi-Z
Remark REST command can be executed one or more times.
Data Sheet E0025N10
45
PD45V128421, 45V128821, 45V128161
/CS Function (Only /CS signal needs to be issued at minimum rate)
( Read latency = 2, Burst length = 4 )
0 CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CKE /CS /RAS /CAS /WE A13 A8,A9,A11,A12 A10 A5,A6,A7 A2,A3,A4 A0,A1
H
Bank Row Row Row Row Row
Bank Channel Channel Channel
Column Column Segment Column
Column Column Column
DQM
L
DQ
Hi-Z
Q1-0
Q1-1
Q1-2
Q1-3
D1-0
D1-1
D1-2 D1-3
Command
ACT
PFC
READ
WRIT
46
Data Sheet E0025N10
PD45V128421, 45V128821, 45V128161
Clock Suspension during Burst Read (using CKE Function)
( Read latency = 2, Burst length = 4 )
0 CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CKE tAPD Command
ACT PFC
tPCD
READ
Channel
Channel 1
Channel 1
Address A13 A10
Row 0 BankA
Segment 1
Col. 0
BankA
without Auto Precharge
DQM
L
DQ
Hi-Z
Q1-0
Q1-1
Q1-2
Q1-3
1 clock suspend
2 clocks suspend
3 clocks suspend
Data Sheet E0025N10
47
PD45V128421, 45V128821, 45V128161
Clock Suspension during Burst Write (using CKE Function)
( Burst length = 4 )
0 CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CKE tAPD Command
ACT PFC
tPCD
WRIT
Channel
Channel 1
Channel 1
Address A13 A10
Row 0 BankA
Segment 1
Col. 0
BankA
without Auto Precharge
DQM
L
DQ
Hi-Z
D1-0
D1-1
D1-2
D1-3
1 clock suspend
2 clocks suspend
3 clocks suspend
48
Data Sheet E0025N10
PD45V128421, 45V128821, 45V128161
Power Down Mode
( Read latency = 2, Burst length = 4 )
0 CLK tCKSP CKE tCKSP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Command
ACT
PFC
READ
PRE
Channel
Channel 1
Channel 1
Address Row 0 A13 BankA A10
Segment 1
Col. 0 BankA
BankA
without Auto Precharge
L
DQM
L
DQ
Hi-Z
Q1-0
Q1-1
Q1-2
Q1-3
Power down mode entry
Power down mode exit
Power down mode entry
Power down mode exit
Active standby
Precharge standby
Data Sheet E0025N10
49
PD45V128421, 45V128821, 45V128161
Read Operation
( Burst length = 4 )
0 CLK 1 2 3 4
Command
READ
Read latency = 2
DQM L
DQ
Hi-Z Q0
Q1
Q2
Q3
Write Operation
0 1 2 3 ( Burst length = 4 )
CLK
Command
WRIT
Write latency = 0
DQM L
DQ
D0
D1
D2
D3
50
Data Sheet E0025N10
PD45V128421, 45V128821, 45V128161
DQM Operation in READ
( Burst length = 4 )
CLK
DQM
Read mask latency = 2
DQ
Hi-Z
Mask
Q0 Q1 Q3
Hi-Z
DQM Operation in WRITE
( Burst length = 4 )
CLK
DQM
Write mask latency = 0
DQ
Mask
D1
Mask
D3
Data Sheet E0025N10
51
PD45V128421, 45V128821, 45V128161
Read to Read Operation
( Read latency = 2, Burst length = 4 )
0 CLK 1 2 3 4 5 6 7 8
Command
READ tCCD
READ
Channel
Channel 1
Channel 3
Address
Col. 0
Col. 0
DQM
L
DQ
Hi-Z
Q1-0
Q1-1
Q1-2
Q1-3
Q3-0
Q3-1
Q3-2
Q3-3
Write to Write Operation
( Burst length = 4 )
0 CLK 1 2 3 4 5 6 7 8
Command
WRIT tCCD
WRIT
Channel
Channel 1
Channel 3
Address
Col. 0
Col. 0
DQM
L
DQ
Hi-Z
D1-0
D1-1
D1-2
D1-3
D3-0
D3-1
D3-2
D3-3
52
Data Sheet E0025N10
PD45V128421, 45V128821, 45V128161
Read to Write Operation
( Burst length = 4 )
0 CLK 1 2 3 4 5 6 7 8
Command
READ tCCD
WRIT
Channel
Channel 1
Channel 3
Address
Col. 0
Col. 0
DQM
L
DQ
Hi-Z
Q1-0
Q1-1
Q1-2
D3-0
D3-1
D3-2
D3-3
Write to Read Operation
( Burst length = 4 )
0 CLK 1 2 3 4 5 6 7 8
Command
WRIT tCCD
READ
Channel
Channel 1
Channel 3
Address
Col. 0
Col. 0
DQM
L
DQ
Hi-Z
D1-0
D1-1
D1-2
Hi-Z
Q3-0
Q3-1
Q3-2
Q3-3
Data Sheet E0025N10
53
PD45V128421, 45V128821, 45V128161
Prefetch to Read Operation without Auto Precharge (Same Channel Read)
( Read latency = 2, Burst length = 4 )
0 CLK tAPD Command ACT PFC tRAS Channel
Channel 1 Channel 1
1
2
3
4
5
6
7
8
tPCD READ PRE tRP ACT
tRC Address A13 A10 Row 0 BankA
Segment
BankA
without Auto Precharge
Col. 0 BankA L
Row 1 BankA
DQM
L
DQ
Hi-Z
Q1-0
Q1-1
Q1-2
Q1-3
Prefetch to Read Operation without Auto Precharge (Other Channel Read)
( Read latency = 2, Burst length = 4 )
0 CLK tPPL Command ACT PFC READ PRE READ 1 2 3 4 5 6 7 8
Channel
Channel 1
Channel 4
Channel 5
Address A13 A10
Row 0 BankA
Segment
BankA
without Auto Precharge
Col. 0 BankA L
Col. 7
DQM
L
DQ
Hi-Z
Q4-0
Q4-1
Q4-2
Q5-7
54
Data Sheet E0025N10
PD45V128421, 45V128821, 45V128161
Prefetch to Write Operation without Auto Precharge (Same Channel Write)
( Burst length = 4 )
0 CLK tAPD Command ACT PFC tRAS Channel
Channel 1 Channel 1
1
2
3
4
5
6
7
8
tPCD WRIT PRE tRP ACT
tRC Address A13 A10 Row 0 BankA
Segment
BankA
without Auto Precharge
Col. 0 BankA L
Row 1 BankA
DQM
L
DQ
Hi-Z
D1-0
D1-1
D1-2
D1-3
Prefetch to Write Operation without Auto Precharge (Other Channel Write)
( Burst length = 4 )
0 CLK tPPL Command ACT PFC WRIT PRE WRIT 1 2 3 4 5 6 7 8
Channel
Channel 1
Channel 4
Channel 3
Address A13 A10
Row 0 BankA
Segment
BankA
without Auto Precharge
Col. 0 BankA L
Col. 7
DQM
L
DQ
Hi-Z
D4-0
D4-1
D4-2
D3-7
D3-8
D3-9
Data Sheet E0025N10
55
PD45V128421, 45V128821, 45V128161
Read to Prefetch to Read Operation without Auto Precharge (Same Channel Prefetch)
( Read latency = 2, Burst length = 4 )
0 CLK tAPD Command READ ACT PFC tPCD Channel
Channel 1 Channel 1 Channel 1
1
2
3
4
5
6
7
8
tPPL READ PRE
Address A13 A10
Col. 0
Row 0 BankA
Segment
BankA
without Auto Precharge
Col. 7 BankA L
DQM
DQ
Hi-Z
Q1-0
Q1-1
Q1-2 Prefetch Termination
Q1-7
Q1-8
Q1-9
Read to Prefetch to Write Operation without Auto Precharge (Same Channel Prefetch)
( Read latency = 2, Burst length = 4 )
0 CLK tAPD Command READ ACT PFC tPCD Channel
Channel 1 Channel 1 Channel 1
1
2
3
4
5
6
7
8
tPPL WRIT PRE
Address A13 A10
Col. 0
Row 0 BankA
Segment
BankA
without Auto Precharge
Col. 3 BankA L
DQM Prefetch Termination DQ Hi-Z Q1-0 Q1-1 D1-3 D1-4 D1-5 D1-6
56
Data Sheet E0025N10
PD45V128421, 45V128821, 45V128161
Write to Prefetch to Write Operation without Auto Precharge (Same Channel Prefetch)
( Burst length = 4 )
0 CLK tAPD Command WRIT ACT PFC tPCD Channel
Channel 1 Channel 1 Channel 1
1
2
3
4
5
6
7
8
tPPL WRIT PRE
Address A13 A10
Col. 0
Row 0 BankA
Segment
BankA
without Auto Precharge
Col. 1 BankA L
DQM MASK DQ Hi-Z D1-0 D1-1 D1-2 D1-3 D1-1 D1-2 D1-3 D1-4
Write to Prefetch to Read Operation without Auto Precharge (Same Channel Prefetch)
( Read latency = 2, Burst length = 4 )
0 CLK tAPD Command WRIT ACT PFC tPCD Channel
Channel 1 Channel 1 Channel 1
1
2
3
4
5
6
7
8
tPPL READ PRE
Address A13 A10
Col. 0
Row 0 BankA
Segment
BankA
without Auto Precharge
Col. 1 BankA L
DQM MASK DQ Hi-Z D1-0 D1-1 D1-2 D1-3 Q1-1 Q1-2
Data Sheet E0025N10
57
PD45V128421, 45V128821, 45V128161
Restore to Read Operation without Auto Precharge (Same Channel Read)
( Read latency = 2, Burst length = 4 )
0 CLK tRCD Command 1 2 3 4 5 6 7 8
RST
tRAD
ACT (R)
tRAS
READ
PRE
Channel
Channel 1
Channel 1
Address A13 A10
Segment BankA
without Auto Precharge
Row 0
Col. 0 BankA L
BankA
DQM
L
DQ
Hi-Z
Q1-0
Q1-1
Q1-2
Remark
ACT(R) command is ACT command after RST command.
Restore to Read Operation without Auto Precharge (Other Channel Read)
( Read latency = 2, Burst length = 4 )
0 CLK 1 2 3 4 5 6 7 8
Command
RST
tRAD
ACT (R)
READ tRAS
Channel 7
PRE
Channel
Channel 1
Address A13 A10
Segment BankA
without Auto Precharge
Row 0
Col. 0 BankA L
BankA
DQM
L
DQ
Hi-Z
Q7-0
Q7-1
Q7-2
Q7-3
Remark
ACT(R) command is ACT command after RST command.
58
Data Sheet E0025N10
PD45V128421, 45V128821, 45V128161
Restore to Write Operation without Auto Precharge (Same Channel Write)
( Burst length = 4 )
0 CLK tRCD Command 1 2 3 4 5 6 7 8
RST
tRAD
ACT (R)
tRAS
WRIT
PRE
Channel
Channel 1
Channel 1
Address A13 A10
Segment BankA
without Auto Precharge
Row 0
Col. 0 BankA L
BankA
DQM
L
DQ
Hi-Z
D1-0
D1-1
D1-2
D1-3
Remark
ACT(R) command is ACT command after RST command.
Restore to Write Operation without Auto Precharge (Other Channel Write)
( Burst length = 4 )
0 CLK 1 2 3 4 5 6 7 8
Command
RST
tRAD
ACT (R)
WRIT tRAS
Channel 3
PRE
Channel
Channel 1
Address A13 A10
Segment BankA
without Auto Precharge
Row 0
Col. 0 BankA L
BankA
DQM
L
DQ
Hi-Z
D3-0
D3-1
D3-2
D3-3
Remark
ACT(R) command is ACT command after RST command.
Data Sheet E0025N10
59
PD45V128421, 45V128821, 45V128161
Read to Restore to Read Operation without Auto Precharge (Same Channel Restore)
( Read latency = 2, Burst length = 4 )
0 CLK tRCD Command READ 1 2 3 4 5 6 7 8
RST
ACT (R)
tRAD tRAS
READ
PRE
Channel
Channel 1
Channel 1
Channel 1
Address A13 A10
Col. 0
Segment BankA
without Auto Precharge
Row 0
Col. 4 BankA L
BankA
DQM
L Restore Termination Q1-0 Q1-1 Q1-4
DQ
Hi-Z
Remark
ACT(R) command is ACT command after RST command.
Read to Restore to Write Operation without Auto Precharge (Same Channel Restore)
( Read latency = 2, Burst length = 4 )
0 CLK tRCD Command READ 1 2 3 4 5 6 7 8
RST
ACT (R)
tRAD tRAS
WRIT
PRE
Channel
Channel 1
Channel 1
Channel 1
Address A13 A10
Col. 0
Segment BankA
without Auto Precharge
Row 0
Col. 5 BankA L
BankA
DQM Restore Termination Q1-0 Q1-1 D1-5 D1-6 D1-7
DQ
Hi-Z
Remark
ACT(R) command is ACT command after RST command.
Data Sheet E0025N10
60
PD45V128421, 45V128821, 45V128161
Write to Restore to Write Operation without Auto Precharge (Same Channel Restore)
( Burst length = 4 )
0 CLK tRCD Command WRIT 1 2 3 4 5 6 7 8
RST
tRAD
ACT (R)
tRAS
WRIT
PRE
Channel
Channel 1
Channel 1
Channel 1
Address A13 A10
Col. 0
Segment BankA
without Auto Precharge
Row 0
Col. 1 BankA L
BankA
DQM MASK DQ D1-0 D1-1 D1-2 Hi-Z Restore Termination D1-1 D1-2
D1-3
Remark
ACT(R) command is ACT command after RST command.
Write to Restore to Read Operation without Auto Precharge (Same Channel Restore)
( Read latency = 2, Burst length = 4 )
0 CLK tRCD Command WRIT 1 2 3 4 5 6 7 8
RST
tRAD
ACT (R)
tRAS
READ
PRE
Channel
Channel 1
Channel 1
Channel 1
Address A13 A10
Col. 0
Segment BankA
without Auto Precharge
Row 0
Col. 1 BankA L
BankA
DQM MASK DQ D1-0 D1-1 D1-2 Hi-Z Restore Termination Q1-1
Remark
ACT(R) command is ACT command after RST command.
Data Sheet E0025N10
61
PD45V128421, 45V128821, 45V128161
Prefetch to Prefetch Operation without Auto Precharge
0 CLK tRRD Command ACT ACT tAPD PFC tPPD PFC tPPD PFC 1 2 3 4 5 6 7 8 9 10
Channel
Channel 1
Channel 8
Channel 2
Address A13 A10
Row 0 BankA
Row 1 BankB
Segment 1
Segment 2
Segment 3
BankB
without Auto Precharge
BankB
without Auto Precharge
BankA
without Auto Precharge
DQM
L
DQ
Hi-Z
Prefetch to Restore Operation without Auto Precharge (Other Bank Restore)
0 CLK tAPD Command ACT PFC tPRD 1 2 3 4 5 6 7 8
RST
tRAD
ACT (R)
Channel
Channel 1
Channel 2
Address A13 A10
Row 0 BankA
Segment 1
Segment 1
Row 0
BankA
without Auto Precharge
BankB
without Auto Precharge
BankB
DQM
L
DQ
Hi-Z
Remark
ACT(R) command is ACT command after RST command.
62
Data Sheet E0025N10
PD45V128421, 45V128821, 45V128161
Prefetch Operation with Auto Precharge
0 CLK tAPD Command ACT PFC A tRC Channel
Channel 1
1
2
3
4
5
6
7
8
9
tPAL ACT
Address A13 A10
Row 0 BankA
Segment 1
Row 0 BankA
BankA Auto Precharge
DQM
L
DQ
Hi-Z
Data Sheet E0025N10
63
PD45V128421, 45V128821, 45V128161
Restore to Prefetch Operation without Auto precharge
0 CLK tRAD Command tRAS 1 2 3 4 5 6 7 8
RST
ACT (R)
RST
ACT (R)
tRAD
PRE tRPD
PFC
tRRDR Channel
Channel 1
Channel 2
Channel 1
Address A13 A10
Segment 1
Row 0
Segment 3
Row 1
Segment 2
BankA
without Auto Precharge
BankA
BankB
without Auto Precharge
BankB
BankA L
BankB
without Auto Precharge
DQM
L
DQ
Hi-Z
Remark
ACT(R) command is ACT command after RST command.
Restore Operation with Auto Precharge
0 CLK tRAD Command tRC 1 2 3 4 5 6 7 8 9
RSTA
ACT (R)
RST
ACT (R)
tRAD
ACT
tRRDR Channel
Channel 2 Channel 1
Address Segment 1 A13 A10
Row 0
Segment 3
Row 1
Row 0 BankA
BankA
Auto Precharge L
BankA
BankB
without Auto Precharge
BankB
DQM
DQ
Hi-Z
Remark
ACT(R) command is ACT command after RST command.
64
Data Sheet E0025N10
PD45V128421, 45V128821, 45V128161
Read to Prefetch Read with Auto Precharge Operation
(Read latency = 2, Prefetch Read latency = 4, Burst length = 4)
0 CLK tAPRD Command tPAL 1 2 3 4 5 6 7 8 9 10 11 12 13
READ
ACT
PFR
tRC
ACT
Channel Channel 1
Channel 1
Illegal to input any other background operation.
Address A13 A10
Col. 8
Row 0 BankA
Col. 0
Segment Segment
Row 1 BankA
DQM
PRL=4 (Prefetch Read Latency) L
READ will be interrupted by PFR.
DQ Hi-Z
Q1-8 Q1-9 Q1-10 Q1-11 Q1-0 Q1-1 Q1-2 Q1-3
Write to Prefetch Read with Auto Precharge Operation
(Read latency = 2, Prefetch Read latency = 4, Burst length = 4)
0 CLK tAPRD Command tPAL 1 2 3 4 5 6 7 8 9 10 11 12
WRIT
ACT
PFR
tRC
ACT
Channel
Channel 1
Channel 1
Illegal to input any other background operation.
Address A13 A10
Col. 8 L
Row 0 BankA
Col. 0
Segment Segment
Row 1 BankA
DQM
PRL=4 (Prefetch Read Latency) L
WRIT will be interrupted by PFR.
DQ
D1-8 D1-9 D1-10
Hi-Z
Q1-0
Q1-1
Q1-2
Q1-3
Data Sheet E0025N10
65
PD45V128421, 45V128821, 45V128161
Auto Refresh Operation
0 CLK tRP Command PALL REF tRCF ACT 1 2 3 4 9 10 11 12
Address A10
H
DQM
L
DQ
Hi-Z
Self Refresh Operation (Entry and Exit)
0 CLK 1 2 3 4 5 6 96 97 98 99 100 101 108 109
CKE tRP Command Address A10
H PALL REF
tRCF
ACT
DQM
L
DQ
Self refresh entry
Self refresh exit
66
Data Sheet E0025N10
PD45V128421, 45V128821, 45V128161
10. Package Drawing
54-PIN PLASTIC TSOP (II) (10.16 mm (400))
54 28
detail of lead end F
P E 1 A H G I S L C D M
M
27
J
N
S
B
K
NOTES 1. Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition. 2. Dimension "A" does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15 mm per side.
ITEM A B C D E F G H I J K L M N P
MILLIMETERS 22.220.05 0.91 MAX. 0.80 (T.P.) 0.32+0.08 -0.07 0.100.05 1.10.1 1.00 11.760.20 10.160.10 0.800.20 0.145+0.025 -0.015 0.500.10 0.13 0.10 3+7 -3 S54G5-80-9JF-2
Data Sheet E0025N10
67
PD45V128421, 45V128821, 45V128161
11. Recommended Soldering Condition
Please consult with our sales offices for soldering conditions of the PD45V128xxx.
Type of Surface Mount Device
PD45V128421G5 : 54-pin Plastic TSOP (II) (10.16mm (400)) PD45V128821G5 : 54-pin Plastic TSOP (II) (10.16mm (400)) PD45V128161G5 : 54-pin Plastic TSOP (II) (10.16mm (400))
68
Data Sheet E0025N10
PD45V128421, 45V128821, 45V128161
12. Revision History
Edition / Date This edition
Page Previous edition Type of revision
Description Location
NEC Corporation (M15076E) 1st edition / Sep. 2000 2nd edition / Sep.2000 p. 2 p. 9 p. 35 p. 39, 40, 42, 43, 44 p. 2 p. 9 p. 35 p. 39, 40, 42, 43, 44 Deletion Modification Deletion Deletion -A10 Block diagram 100 MHz -A10 specs - - - -
Elpida Memory, Inc. (E0025N) 1st edition / Jan. 2001 - - - Republished by Elpida Memory, Inc.
Data Sheet E0025N10
69
PD45V128421, 45V128821, 45V128161
[MEMO]
70
Data Sheet E0025N10
PD45V128421, 45V128821, 45V128161
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
Data Sheet E0025N10
71
PD45V128421, 45V128821, 45V128161
[MEMO]
The names of the companies, products, and logos described herein are the trademarks or registered trademarks of each company.
* The information in this document is current as of November, 2000. The information is subject to change without notice. For actual design-in, refer to the latest publications of Elpida's data sheets or data books, etc., for the most up-to-date specifications of Elpida semiconductor products. Not all products and/or types are available in every country. Please check with an Elpida Memory, Inc. for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without prior written consent of Elpida. Elpida assumes no responsibility for any errors that may appear in this document. * Elpida does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of Elpida semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. Elpida assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While Elpida endeavours to enhance the quality, reliability and safety of Elpida semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in Elpida semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. * Elpida semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of Elpida semiconductor products is "Standard" unless otherwise expressly specified in Elpida's data sheets or data books, etc. If customers wish to use Elpida semiconductor products in applications not intended by Elpida, they must contact an Elpida Memory, Inc. in advance to determine Elpida's willingness to support a given application. (Note) (1) "Elpida" as used in this statement means Elpida Memory, Inc. and also includes its majority-owned subsidiaries. (2) "Elpida semiconductor products" means any semiconductor product developed or manufactured by or for Elpida (as defined above).
M8E 00. 4

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